Solved by verified expert:A. Creating a new folder in your home directory
1. Make sure you are at your home directory by typing
cd
2. At your home directory create a new directory named tsmc018 by typing
mkdir tsmc018
B. Copying files to the new folder
1. Change directory to the tsmc018 by typing
cd tsmc018
2. Copy the following three files: (a) .cdsinit, (b) display.drf, and (c) cds.lib by typing
a. cp $CDK_DIR/cdssetup/cdsinit .
b. cp ../../../usr/cadence/tsmc/CR018G1P6M/1P6M_4X1U/display.drf .
c. cp ../../../usr/cadence/tsmc/CR018G1P6M/1P6M_4X1U/cds.lib .
C. Opening Cadence and Modifying the Library
1. Open Cadence by typing
virtuoso &
2. Add the path of the TSMC018 Library in your Library Manager and then saveSee the attachment below..
ee_530_cadence_assignment_3_1_.pdf
Unformatted Attachment Preview
EE 530 Cadence Assignment 3
IMPORTANT:
–
This assignment is not a group project. Collaborations are encouraged but every student is
required to do this assignment alone and submit a report.
Due date is 4/2/2018.
In a few days, I will announce Task 3 and Task 4, which won’t involve design but rather
schematics-based simulations.
Task 1: Setting up Cadence for TSMC 0.18 µm process
A. Creating a new folder in your home directory
1. Make sure you are at your home directory by typing
cd
2. At your home directory create a new directory named tsmc018 by typing
mkdir tsmc018
B. Copying files to the new folder
1. Change directory to the tsmc018 by typing
cd tsmc018
2. Copy the following three files: (a) .cdsinit, (b) display.drf, and (c) cds.lib by typing
a. cp $CDK_DIR/cdssetup/cdsinit .
b. cp ../../../usr/cadence/tsmc/CR018G1P6M/1P6M_4X1U/display.drf .
c. cp ../../../usr/cadence/tsmc/CR018G1P6M/1P6M_4X1U/cds.lib .
C. Opening Cadence and Modifying the Library
1. Open Cadence by typing
virtuoso &
2. Add the path of the TSMC018 Library in your Library Manager and then save.
After saving, close the Library Path Editor. At this point, verify you have the contents of tsmc18
library in your Library Manager as highlighted with the red box below:
D. Running a dc sweep of a PMOS
1. Create a new Library named pmos
E. Create a new cellview named pmos
F. In the empty schematics window, hit the shortcut i to add a pmos device from the tsmc18 library.
Note: We will use pmos2v and nmos2v devices in our designs.
G. Place the pmos in the schematics and add independent sources and globals (e.g., gnd) for gate
sweep simulations.
You label a wire by using the shortcut l (for label) and universal voltages (vdd and ground) are labeled as
vdd! and gnd! Note Vdc=1.8 V.
H. Run a .dc simulation
1. Launch ADE L
2. In the ADE L window select spectre as the simulator from Setup>Simulator/Directory/Host
3. In the ADE L window select pmos schematics under pmos library as the Design file from
Setup>Design…
4. In the ADE L window setup the Model Library Files as below after selecting Setup>Model
Libraries…
After entering the .scs Model File, it is very important to select the Section as tt (meaning analysis
for the typical-typical corner condition)
I.
J.
In the ADE L window, select Variables>Copy From Cellview and set vg a value of 1
Create a dc analysis with the following settings. Select the current entering into the source of the
pmos as the output to be plotted. Run the simulation.
You should get something like:
K. Now do a vsd sweep for several vsg values (Parametric Analysis). Note the changes in the dc sources
and the ADE L window. Dc analysis variable is the vd source. Parametric analysis variable is the vg
source.
You should get something like:
Task 2: Designing a Two-Stage Operational Amplifier
Design the two-stage op-amp above with single supply (1.8 V) above. For bias generation, use the circuit
to the right of op-amp after properly designing Q8. For , , , ℎ, , ℎ, refer to the
nmospmosmodels.docx file. The important values are bolded in the file.
′
Units are , : 2 / , : ,
=
2 0
, 2 = 3.9, 0 = 8.854 10−12 , , : 0 in the file.
A. Minimum Specifications:
a. DC Gain > 60 dB
b. Unity-Gain Bandwidth > 10 MHz (when a load capacitance CL=1 pF is connected at the
output)
c. Phase-Margin > 60˚
d. Slew Rate > 10 V/µs
e. Input Common-Mode Range > 1 V
f. Output Swing > 1.5 V
g. CMRR > 70 dB
h. Power Consumption < 100 µW (Only the op-amp - bias generation power excluded)
B. Simulate your op-amp and verify the design specifications.
Note: As for model files of nmos/pmos devices and capacitors, make sure to include the following in
your model library setup with proper “Section” selection:
a. For dc gain, unitygain bandwidth,
and phase-margin
simulations do an
.ac analysis
between 1 Hz and
100 GHz with
logarithmic
sweep of 1000
points. Plot the
AC gain – phase
and use that plot
for verifying the
specs. Use a
differential input
signal as on the
right. The source
connected to vp
has AC
Magnitude: 1 V.
The other one
has 0 V.
b. For CMRR, do an .ac analysis with two copies of your op-amps: one with a differential input
(as in part a) and the other with both inputs connected to the same source with AC
Magnitude: 1V. Repeat the same .ac analysis as above. Plot the AC gain-phase by selecting
the output node of the differentially connected opamp as the first point, and the output
node of the common-mode connected opamp as the second point.
c. For input common-mode range, do an .ac analysis for a differential input signal with a
common-mode dc signal varying from 0 V to 1.8 V. For that use parametric analysis with a
total step size of 40. The common-mode voltage range that make your design to provide
your target dc gain value would be your ICMR.
d. For output swing simulation, do a 1 s transient analysis when your op-amp is in unity-gain
(buffer) configuration. The input is a triangular voltage varying from 0V to 1.8 V in 1 s.
Determine the output voltage range your op-amp can provide without distortion.
e. For slew rate simulation, do a 1 s transient analysis when your op-amp is in unity-gain
(buffer) configuration. The input is a square wave with parameters below (300 mV change in
1 ps). Measure the slopes for both rising edge and falling edge. Example input/output
waveforms are shown for rising edge.
f.
For power measurement, simulate the currents through Q5 and Q7.
Task 3: Floating-Gate PMOS Devices: To be announced in a few days.
Task 4 (Extra Credit): Peak-Detector Circuit: To be announced in a few days.
...
Purchase answer to see full
attachment
